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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com CS42406 24-bit, 192 khz 2-in 6-out audio codec d/a features 24-bit conversion 102 db dynamic range at 5 v -91 db thd+n digital volume control with soft ramp ? 119 db attenuation ? 1 db step size ? zero crossing click-free transitions i2c & spi ? host control port atapi mixing low clock jitter sensitivity popguard technology ? for control of clicks and pops a/d features 24-bit conversion 105 db dynamic range at 5 v -98 db thd+n advanced multi-bit delta-sigma architecture high pass filter to remove dc offsets auto-mode selection system features direct interface with 5 v to 1.8 v logic levels supports independent, synchronous adc/dac sample rates operation as clock master or slave supports all audio sample rates including 192 khz single-ended inputs/outputs analog/digital core supplies from 3.3 v to 5v vlc = 1.8 v to 5 v mute controls ? modulators anti-alias filter external mute control register / hardware configuration internal voltage reference mixers interpolation filters pdn/reset switched capacitor dacs and filters multibit oversampling adc multibit oversampling adc anti-alias filter high pass filter high pass filter pcm serial interface left input right input volume controls level translator level translator serial audio input/output vd = 3.3 v to 5 v hardware or i 2 c/spi control data va = 3.3 v to 5 v analog outputs vls 1.8 v to 5 v dec ?04 ds614pp5
CS42406 2 ds614pp5 stand alone mode feature set system features ? adc serial audio port master or slave operation ? independent adc and dac reset/power-down ? 256x or 384x mclk/lrck ratio selectable d/a features ? auto-mute on static samples ? 44.1 khz 50/15 s de-emphasis available ? selectable serial audio interface formats left justified up to 24-bit data i2s up to 24-bit data right justified, 16-bit data right justified, 24-bit data a/d features ? serial audio port master or slave operation ? auto-mode select in slave mode ? high-pass filter ? selectable serial audio interface formats left justified up to 24-bit i2s up to 24-bit data control port mode feature set d/a features ? selectable auto-mute ? selectable 32, 44.1, and 48 khz de-emphasis filters ? configurable atapi mixing functions ? configurable volume and muting controls ? selectable serial audio interface formats left justified up to 24-bit i2s up to 24-bit right justified 16, 18, 20, and 24-bit general description the CS42406 is a low cost, integrated audio co- dec. the CS42406 performs stereo analog-to- digital (a/d) conversion and six channels of digital- to-analog (d/a) conversion of up to 24-bit serial values at sample rates up to 200 khz. the d/a offers a volume control that operates with a 1 db step size. it incorporates selectable soft ramp and zero crossing transition functions to elim- inate clicks and pops. the d/a?s integrated digital mixing functions allow a variety of output configurations ranging from a channel swap to a stereo-to-mono down-mix. standard 50/15 s de-emphasis is available for sampling rates of 32, 44.1, and 48 khz for compat- ibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. integrated level translators allow easy interfacing between the CS42406 and other devices operating over a wide range of logic levels. high-pass filters are available for the right and left channel of the a/d. this allows the a/d to remove unwanted dc offsets. the CS42406?s wide dynamic range, negligible distortion, and low noise make it ideal for applica- tions such as a/v receivers, dvd receivers, and set-top box systems. ordering information CS42406-cqz -10 to 70 c 48-pin lqfp cdb42406 evaluation board
CS42406 3 table of contents 1. pin description ........................................................................................................... ........ 6 2 characteristics and specifications ......................................................................... 8 specified operating conditions................................................................................. 8 absolute maximum ratings ........................................................................................... 8 dac analog characteristics (CS42406-cqz)............................................................ 9 dac filter response...................................................................................................... 11 adc analog characteristics (CS42406-cqz).......................................................... 14 adc digital filter response....................................................................................... 16 dc electrical characteristics ................................................................................ 19 digital characteristics............................................................................................... 20 switching characteristics - dac serial audio port ........................................ 21 switching characteristics - adc serial audio port ........................................ 23 switching specifications - control port interface ....................................... 27 3. typical connection diagram .................................................................................... 29 4. applications .............................................................................................................. ....... 30 4.1 single, double, and quad-speed modes ........................................................................ 30 4.1.1 adc serial port ................................................................................................... 30 4.1.2 dac serial port ................................................................................................... 30 4.1.2a stand alone mode ............................................................................... 30 4.1.2b control port mode ................................................................................ 31 4.2 adc serial port operation as either a clock master or slave ........................................ 31 4.2.1 operation as a clock master .............................................................................. 31 4.2.2 operation as a clock slave ................................................................................ 32 4.3 digital interface format .................................................................................................. .32 4.3.1 dac serial port ................................................................................................... 32 4.3.1a stand alone mode ............................................................................... 33 4.3.1b control port mode ............................................................................... 33 4.3.2 adc serial port ................................................................................................... 33 4.4 de-emphasis control ...................................................................................................... 3 3 4.4.1 stand alone mode .............................................................................................. 33 4.4.2 control port mode ............................................................................................... 33 4.5 analog connections ........................................................................................................ 34 4.5.1 capacitor size on the reference pin (filt+) ..................................................... 34 4.6 recommended power-up sequence ............................................................................... 35 4.6.1 stand alone mode .............................................................................................. 35 4.6.2 control port mode ............................................................................................... 35 4.7 popguard ? transient control .......................................................................................... 35 4.7.1 power-up ............................................................................................................. 35 4.7.2 power-down ........................................................................................................ 35 4.7.3 discharge time ................................................................................................... 35 4.8 mute control .............................................................................................................. ...... 36 4.9 grounding and power supply arrangements .................................................................. 36 4.9.1 capacitor placement ........................................................................................... 36 4.10 control port interface ................................................................................................... .36 4.10.1 memory address pointer (map) ....................................................................... 36 4.10.1a incr (auto map increment) .............................................................. 37 4.10.1b map0-3 (memory address pointer) ................................................... 37 4.10.2 i2c mode ........................................................................................................... 37 4.10.2a i2c write ............................................................................................. 37 4.10.2b i2c read ............................................................................................. 37
CS42406 4 ds614pp5 4.10.3 spi mode .......................................................................................................... 38 4.10.3a spi write ............................................................................................ 38 5. register quick reference ......................................................................................... 40 6. register descriptions .................................................................................................. 41 6.1 mode control 1 (address 01h) ......................................................................................... 41 6.2 invert signal (address 02h).............................................................................................. 4 2 6.3 mixing control pair 1 (channels a1 & b1) (address 03h) mixing control pair 2 (channels a2 & b2) (address 04h) mixing control pair 3 (channels a3 & b3) (address 05h) ............................................. 42 6.4 volume control (addresses 06h - 0bh) ............................................................................ 44 6.5 mode control 2 (address 0ch).......................................................................................... 44 7 parameter definitions ................................................................................................... 47 8. package dimensions ....................................................................................................... 4 8 9. revision history .......................................................................................................... .... 49 list of figures figure 1. output test load ..................................................................................................... .... 10 figure 2. maximum loading ...................................................................................................... .. 10 figure 3. single-speed stopband rejection ............................................................................... 12 figure 4. single-speed transition band ..................................................................................... 12 figure 5. single-speed transition band (detail) ......................................................................... 12 figure 6. single-speed passband ripple ................................................................................... 12 figure 7. double-speed stopband rejection .............................................................................. 12 figure 8. double-speed transition band .................................................................................... 12 figure 9. double-speed transition band (detail) ....................................................................... 12 figure 10. double-speed passband ripple .................................................................................. 12 figure 11. single-speed mode stopband rejection ..................................................................... 16 figure 12. single-speed mode stopband rejection ..................................................................... 16 figure 13. single-speed mode transition band (detail) ............................................................... 16 figure 14. single-speed mode passband ripple ......................................................................... 16 figure 15. double-speed mode stopband rejection .................................................................... 16 figure 16. double-speed mode stopband rejection .................................................................... 16 figure 17. double-speed mode transition band (detail) ............................................................. 17 figure 18. double-speed mode passband ripple ........................................................................ 17 figure 19. quad-speed mode stopband rejection ...................................................................... 17 figure 20. quad-speed mode stopband rejection ...................................................................... 17 figure 21. quad-speed mode transition band (detail) ................................................................ 17 figure 22. quad-speed mode passband ripple ........................................................................... 17 figure 23. dac serial audio port ............................................................................................... ... 21 figure 24. master mode, left justified sai ................................................................................... 24 figure 25. slave mode, left justified sai ..................................................................................... 2 4 figure 26. master mode, i2s sai ................................................................................................ ... 24 figure 27. slave mode, i2s sai ................................................................................................. .... 24 figure 28. left justified up to 24-bit data .................................................................................... .25 figure 29. i2s, up to 24-bit data .............................................................................................. ...... 25 figure 30. right justified data ................................................................................................ ...... 25 figure 31. control port timing - i2c mode .................................................................................... 26 figure 32. control port timing - spi mode ................................................................................... 27 figure 33. typical connection diagram ........................................................................................ 28
CS42406 5 figure 34. adc serial port, master mode clocking ...................................................................... 31 figure 35. de-emphasis curve ................................................................................................... .. 32 figure 36. CS42406 recommended analog input buffer ............................................................. 33 figure 37. CS42406 adc: thd+n versus frequency .................................................................. 33 figure 38. i2c write ........................................................................................................... ............ 36 figure 39. i2c read ............................................................................................................ ........... 37 figure 40. spi write ........................................................................................................... ........... 37 figure 41. atapi block diagram ................................................................................................. .41 list of tables table 1. adc speed modes and the associated output sample rates (fs) for 256x mode .......... 29 table 2. adc speed modes and the associated output sample rates (fs) for 384x mode .......... 29 table 3. CS42406 stand alone dac operational modes ................................................................ 30 table 4. CS42406 control port dac operational modes ................................................................ 30 table 5. CS42406 adc serial port mode control ........................................................................... 30 table 6. dac digital interface format - stand alone mode............................................................. 32 table 7. digital interface formats - control port mode.................................................................... 39 table 8. atapi decode.......................................................................................................... .......... 41 table 9. example digital volume settings ....................................................................................... 42 table 10. revision history ..................................................................................................... .......... 47
CS42406 6 ds614pp5 1. pin description pin name # pin description dac_sclk 1 dac serial clock ( input ) - serial clock for the dac serial audio interface. dac_lrck 2 dac left right clock ( input ) - determines which channel, left or right, is currently active on the dac serial audio data line. mclk 3 master clock ( input ) - clock source for the delta-sigma modulators and digital filters. vls 4 45 serial audio interface power ( input ) - positive power for the serial audio interface. sdout 5 serial audio data output (output) - output for two?s complement serial audio data. adc_384x/256x 6 adc mclk/lrck ratio select (input) - selects the base mclk/lrck ratio for the adc serial port. vd 7 9 digital power ( input ) - positive power supply for the digital section. gnd 8 31 33 ground ( input ) rst_dac 10 dac reset ( input ) - powers down the dac and resets all internal resisters to their default settings. adc_sclk 11 adc serial clock ( input/output ) - serial clock for the adc serial audio interface. adc_lrck 12 adc left right clock ( input/output ) - determines which channel, left or right, is currently active on the adc serial audio data line. vlc 16 control port interface power ( input ) - positive power for the control port interface. adc_pdn 18 adc power-down (input) - the adc enters a low power mode when low. tst 19,20 23,27 35,42 test pin (input) - connect to gnd. dif1/scl/cclk gnd gnd aoutb3 tst adc_filt+ va aouta3 mutec3 6 2 4 8 10 1 3 5 7 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 adc_384x/256x dac_lrck vls gnd dac_rst dac_sclk mclk sdout vd adc_sclk adc_lrck vd adc_m0 sdin3 tst sdin2 CS42406 sdin1 vls dif0/sda/cdin dac_m0/ad0/cs vlc adc_pdn tst tst dac_filt+ dac_vq dac_m1 tst aoutb2 mutec2 aouta2 aouta1 aoutb1 mutec1 adc_m1 ainr adc_vq ainl tst
CS42406 7 dac_filt+ 21 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. dac_vq 22 quiescent voltage ( output ) - filter connection for internal quiescent voltage. ainl ainr 24 26 analog inputs (input) - the full scale analog input level is specified in the ?adc analog character- istics (CS42406-cqz)? on page 14. adc_vq 25 quiescent voltage ( output ) - filter connection for internal quiescent voltage. aoutb3 aouta3 aoutb2 aouta2 aoutb1 aouta1 29 30 36 37 39 40 analog outputs ( output ) - the full scale analog line output level is specified in the ?dac analog characteristics (CS42406-cqz)? on page 9. mutec3 mutec2 mutec1 28 38 41 mute control ( output ) - control signals for optional mute circuit. va 32 analog power ( input ) - positive power supply for the analog section. adc_filt+ 34 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. adc_m1 adc_m0 43 44 adc mode selection ( input ) - determines the operational speed mode of the adc. sdin1 sdin2 sdin3 46 47 48 serial audio data input ( input ) - input for two?s complement serial audio data. dac control port definitions scl/cclk 13 serial control port clock ( input ) - serial clock for the control port interface. sda/cdin 14 serial control data i/o ( input/output ) - input/output for i2c data. input for spi data. ad0/cs 15 address bit / chip select ( input ) - chip address bit in i2c mode. control signal used to select the chip in spi mode. dac stand alone defini- tions dif1 dif0 13 14 digital interface format ( input ) - defines the required relationship between the left right clock, serial clock and serial audio data for the dac. dac_m0 dac_m1 15 17 mode selection ( input ) - determines the operational speed mode of the dac.
CS42406 8 ds614pp5 2 characteristics and specifications (all min/max characteristics and specifications are guaranteed over the specified operating conditions. typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and t a = 25 c.) specified operating conditions (gnd = 0 v, all voltages with respect to 0 v.) notes: 1. this part is specified at typical analog voltages of 3.3 v and 5.0 v. see dac analog characteristics (CS42406-cqz) and adc analog characteristics (CS42406-cqz) for details. 2. nominal vd supply must be less than or equal to the nominal va supply. 3. in 384x mode for the adc, quad-speed slave mode operation is limited to a nominal va and vd of 5 v. 4. in 384x mode for the adc, double-speed & quad-speed mode operation is limited to a minimum vl of 2.5 v absolute maximum ratings (gnd = 0 v, all voltages with respect to ground.) (note 7) notes: 5. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause src latch-up. 6. the maximum over/under voltage is limited by the input current. 7. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit power supplies analog (note 3) digital (note 2, 3) logic/serial interface (note 4) control port interface va vd vls vlc 3.1 3.1 1.7 1.7 (note 1) 3.3 3.3 3.3 5.25 5.25 5.25 5.25 v v v v ambient temperature commercial -cqz t a -10 - +70 c parameter symbol min max units dc power supplies: analog digital serial audio interface (sai) control port interface va vd vls vlc -0.3 -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 +6.0 v v v v input current (note 5) i in - 10 ma analog input voltage (note 6) v in gnd-0.7 va+0.7 v digital input voltage(note 6) serial audio data interface control port interface v ind_s v ind_s -0.3 -0.3 vls+0.4 vlc+0.4 v v ambient operating temperature (power applied) t a -50 +95 c storage temperature t stg -65 +150 c
CS42406 9 dac analog characteristics (CS42406-cqz) test conditions (unless otherwise specified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth is 10 hz to 20 khz; test load r l = 10 k ? , c l = 10 pf (see figure 1). notes: 8. one-half lsb of triangular pdf dither is added to data. parameter va = 5.0 v va = 3.3 v min typ max min typ max unit single-speed mode fs = 48 khz dynamic range (note 8) unweighted a-weighted 93 96 99 102 - - 88 91 94 97 - - db db total harmonic distortion + noise (note 8) 0 db -20 db -60 db - - - -91 -79 -39 -85 - - - - - -91 -74 -34 -85 - - db db db double-speed mode fs = 96 khz dynamic range (note 8) unweighted a-weighted 40 khz bandwidth a-weighted 93 96 - 99 102 100 - - - 88 91 - 94 97 97 - - - db db db total harmonic distortion + noise (note 8) 0 db -20 db -60 db - - - -91 -79 -39 -85 - - - - - -91 -74 -34 -85 - - db db db quad-speed mode fs = 192 khz dynamic range (note 8) unweighted a-weighted 40 khz bandwidth a-weighted 93 96 - 99 102 100 - - - 88 91 - 94 97 97 - - - db db db total harmonic distortion + noise (note 8) 0 db -20 db -60 db - - - -91 -79 -39 -85 - - - - - -91 -74 -34 -85 - - db db db
CS42406 10 ds614pp5 dac analog characteristics (CS42406-cqz) (continued) 9. see figure 1-2. r l and c l reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. in this circuit topology, c l will effectively move the dominant pole of the two-pole amp in the output stage. increasing this value beyond the recommended 100 pf can cause the internal op-amp to become unstable. . parameters symbol min typ max units dynamic performance for all modes interchannel isolation (1 khz) - 102 - db dc accuracy interchannel gain mismatch icgm - 0.1 - db gain drift - 100 - ppm/c analog output characteristics and specifications full scale output voltage 0.60va 0.66va 0.72va vpp output impedance z out - 100 - ? minimum ac-load resistance (note 7) r l -3-k ? maximum load capacitance (note 7) c l - 100 - pf aoutx agnd 3.3 f v out r l c l + figure 1. output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 figure 2. maximum loading
CS42406 11 dac filter response the filter characteristics and the x-axis of the response plots have been nor- malized to the input sample rate (fs) and can be referenced to the desired sample rate by multiplying the given char- acteristic by fs. notes: 10. for single-speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 11. de-emphasis is only available in single-speed mode. parameter min typ max unit single-speed mode - (4 khz to 50 khz sample rates) passband to -0.05 db corner to -3 db corner 0 0 - - 0.4535 0.4998 fs fs passband ripple -0.02 - +0.035 db stopband 0.5465 - - fs stopband attenuation (note 10) 50 - - db group delay - 9/fs - s de-emphasis error (relative to 1 khz) (note 11) control port mode fs = 32 khz fs = 44.1 khz fs = 48 khz stand-alone mode fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - - - - - - - +0.2/-0.1 +0.05/-0.14 +0/-0.22 +1.5/-0 +0.05/-0.14 +0.2/-0.4 db db db db db db double-speed mode - (50 khz to 100 khz sample rates) passband to -0.1 db corner to -3 db corner 0 0 - - 0.4621 0.4982 fs fs passband ripple -0.1 - 0 db stopband 0.577 - - fs stopband attenuation (note 10) 55 - - db group delay - 4/fs - s quad-speed mode - (100 khz to 200 khz sample rates) passband to -3 db corner 0 - 0.25 fs passband ripple -0.7 - 0 db group delay - 1.5/fs - s
CS42406 12 ds614pp5 figure 3. single-speed stopband rejection figure 4. single-speed transition band figure 5. single-speed transition band (detail) figure 6. single-speed passband ripple figure 7. double-speed stopband rejection figure 8. double-speed transition band
CS42406 13 figure 9. double-speed transition band (detail) figure 10. double-speed passband ripple
CS42406 14 ds614pp5 adc analog characteristics (CS42406-cqz) test conditions (unless otherwise specified): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz. note: 12. referred to the typical full-scale input voltage parameter va = 5.0 v va = 3.3 v min typ max min typ max unit single-speed mode fs = 48 khz dynamic range unweighted a-weighted 96 99 102 105 - - 93 96 99 102 - - db db total harmonic distortion + noise (note 12) -1 db -20 db -60 db - - - -98 -82 -42 -92 - - - - - -95 -79 -39 -89 - - db db db double-speed mode fs = 96 khz dynamic range unweighted a-weighted 40 khz bandwidth unweighted 96 99 - 102 105 99 - - - 93 96 - 99 102 96 - - - db db db total harmonic distortion + noise (note 12) -1 db -20 db -60 db - - - -98 -82 -42 -92 - - - - - -95 -79 -39 -89 - - db db db quad-speed mode fs = 192 khz dynamic range unweighted a-weighted 40 khz bandwidth unweighted 96 99 - 102 105 99 - - - 93 96 - 99 102 96 - - - db db db total harmonic distortion + noise (note 12) -1 db -20 db -60 db - - - -98 -82 -42 -92 - - - - - -95 -79 -39 -89 - - db db db
CS42406 15 adc analog characteristics (CS42406-cqz) (continued) parameters min typ max units dynamic performance for all modes interchannel isolation - 90 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error - - 10 % gain drift - 100 - ppm/c analog input characteristics full scale input voltage 0.53va 0.56va 0.59va vpp input impedance 18 - - k ?
CS42406 16 ds614pp5 adc digital filter response the filter characteristics and the x-axis of the response plots have been normalized to the sample rate (fs) and can be referenced to the desired sample rate by multiplying the given characteristic by fs . note: 13. response shown is for fs equal to 48 khz. parameter min typ max unit single-speed mode (4 khz to 50 khz sample rates) passband to -0.1 db corner 0 - 0.49 fs passband ripple - - 0.035 db stopband 0.57 - - fs stopband attenuation 70 - - db total group delay - 12/fs - s double-speed mode (50 khz to 100 khz sample rates) passband to -0.1 db corner 0 - 0.49 fs passband ripple - - 0.025 db stopband 0.56 - - fs stopband attenuation 69 - - db total group delay - 9/fs - s quad-speed mode (100 khz to 200 khz sample rates) passband to -0.1 db corner 0 - 0.26 fs passband ripple - - 0.025 db stopband 0.50 - - fs stopband attenuation 60 - - db total group delay - 5/fs - s high pass filter characteristics frequency response -3.0 db -0.13 db (note 13) -1 20 - - hz hz phase deviation @ 20 hz (note 13) - 10 - deg passband ripple - - 0 db
CS42406 17 figure 11. single-speed mode stopband rejection figure 12. single-speed mode stopband rejection figure 13. single-speed mode transition band (detail) figure 14. single-speed mode passband ripple figure 15. double-speed mode stopband rejection figure 16. double-speed mode stopband rejection -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 .0 0 .1 0 .2 0 .3 0.4 0.5 0.6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (norm alized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (norm alized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 .0 0 .1 0 .2 0 .3 0.4 0.5 0.6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db)
CS42406 18 ds614pp5 figure 17. double-speed mode transition band (detail) figure 18. double-speed mode passband ripple figure 19. quad-speed mode stopband rejection figure 20. quad-speed mode stopband rejection figure 21. quad-speed mode transition band (detail) figure 22. quad-speed mode passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (norm alized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (norm alized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 .0 0 .1 0 .2 0 .3 0.4 0.5 0.6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 - 110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (norm alized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 frequency (normalized to fs) amplitude (db)
CS42406 19 dc electrical characteristics gnd = 0 v; all voltages with respect to gnd. notes: 14. normal operation is defined as rst = hi with a 997 hz, 0 dbfs digital input sampled at the highest f s for each speed mode, and open outputs, unless otherwise specified. analog inputs are driven with a 1 khz, -1 dbfs sine wave and sampled at the highest f s for each speed mode. 15. i dt measured with no external loading on pin 14 (sda). 16. power down mode is defined as dac_rst = lo, pdn_adc = lo, with all clocks and data lines held static. 17. valid with the recommended capacitor values on filt+ and vq as shown in figure 33. parameters symbol min typ max units normal operation (note 14) power supply current va = 5.0 v vd, vls, vlc = 5.0 v va = 3.3 v vd, vls, vlc = 3.3 v (note 15) i a i dt i a i dt - - - - 43 40 40 25 48 45 44 26 ma ma ma ma power dissipation all supplies = 5.0 v all supplies = 3.3 v - - 415 215 465 231 mw mw power-down mode (note 16) power supply current all supplies = 5.0 v all supplies = 3.3 v - - 2 1 - - ma ma power dissipation all supplies = 5.0 v all supplies = 3.3 v - - 10 3.3 - - mw mw all modes of operation power supply rejection ratio (note 17) 1 khz psrr - 60 - db v q nominal voltage output impedance dac_vq adc_vq maximum allowable dc current source/sink - - - - 0.5va 250 25 0.01 - - - - v k ? k ? ma filt+ nominal voltage - va - v mutec low-level output voltage - 0 - v mutec high-level output voltage - va - v maximum mutec drive current - 3 - ma
CS42406 20 ds614pp5 digital characteristics gnd = 0 v; all voltages with respect to gnd. parameters symbol min typ max units input leakage current i in --10 a input capacitance - 8 - pf high-level input voltage (% of vls/vlc) v ih 70% - - v low-level input voltage (% of vls/vlc) v il --13%v high-level output voltage at i o = 100 a (% of vls/vlc) v oh 70% - - v low-level output voltage at i o =100 a (% of vls/vlc) v ol --15%v
CS42406 21 switching characteristics - dac serial audio port (logic ?0? = gnd = 0 v, logic ?1? = vls) * for a description of speed modes, please refer to section 4.1.2 on page 30. parameter symbol min typ max unit mclk specifications mclk frequency 1.024 - 12.8 mhz 22 - 25.6 mhz mclk duty cycle 45 - 55 % single-speed* dac_lrck duty cycle 45 - 55 % dac_sclk frequency - - 128 fs hz dac_sclk pulse width low t sclkl 20 - - ns dac_sclk pulse width high t sclkh 20 - - ns dac_sclk rising to dac_lrck edge delay t slrd 20 ns dac_sclk rising to dac_lrck edge setup time t slrs 20 ns sdinx valid to dac_sclk rising setup time t sdlrs 20 ns dac_sclk rising to sdinx hold time t sdh 20 ns double-speed* dac_lrck duty cycle 45 - 55 % dac_sclk frequency - - 64 fs hz dac_sclk pulse width low t sclkl 20 - - ns dac_sclk pulse width high t sclkh 20 - - ns dac_sclk rising to dac_lrck edge delay t slrd 20 ns dac_sclk rising to dac_lrck edge setup time t slrs 20 ns sdinx valid to dac_sclk rising setup time t sdlrs 20 ns dac_sclk rising to sdinx hold time t sdh 20 ns quad-speed* dac_lrck duty cycle 45 - 55 % dac_sclk frequency - - mclk/2 hz dac_sclk pulse width low t sclkl 20 - - ns dac_sclk pulse width high t sclkh 20 - - ns dac_sclk rising to dac_lrck edge delay t slrd 20 ns dac_sclk rising to dac_lrck edge setup time t slrs 20 ns sdinx valid to dac_sclk rising setup time t sdlrs 20 ns dac_sclk rising to sdinx hold time t sdh 20 ns
CS42406 22 ds614pp5 figure 23. dac serial audio port sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdinx dac_sclk dac_lrck
CS42406 23 switching characteristics - adc serial audio port logic ?0? = gnd = 0 v; logic ?1? = vls, c l = 20 pf. note: certain parameters depend on the 256x/384x (pin6) mode setting and are separated below. parameter symbol min typ max unit mclk duty cycle 45 - 55 % master mode adc_sclk falling to adc_lrck t mslr -20 - 20 ns adc_sclk falling to sdout valid t sdo 0 - 32 ns slave mode single-speed* adc_lrck frequency mclk = 256, 384 fs (1 or 1.5) (note 18) mclk = 512, 768 fs (2 or 3) fs fs 4 43 -50 50 khz khz adc_lrck duty cycle 40 - 60 % sdout valid before adc_sclk rising t stp 10 - - ns sdout valid after adc_sclk rising t hld 5- -ns adc_sclk falling to adc_lrck edge t slrd -20 - 20 ns double-speed* adc_lrck frequency mclk = 128, 192 fs (1 or 1.5) (note 18) mclk = 256, 384 fs (2 or 3) fs fs 50 86 -100 100 khz khz adc_lrck duty cycle 40 - 60 % sdout valid before adc_sclk rising t stp 10 - - ns sdout valid after adc_sclk rising t hld 5- -ns adc_sclk falling to adc_lrck edge t slrd -20 - 20 ns quad-speed* adc_lrck frequency (note 18) mclk = 128 fs (2 or 3) fs 172 - 200 khz adc_lrck duty cycle 40 - 60 % sdout valid before adc_sclk rising t stp 10 - - ns sdout valid after adc_sclk rising t hld 5- -ns adc_sclk falling to adc_lrck edge t slrd -8 - 8 ns
CS42406 24 ds614pp5 * for a description of speed modes, please refer to table 1 on page 30. 18. internal is automatically determined when operating within the specified limits. 256x mode (pin 6 = lo) mclk frequency (note 18) internal 1 1.024 - 12.8 mhz internal 2 22.016 - 25.6 mhz master mode adc_sclk duty cycle single-speed mode double-speed mode quad-speed mode - - - 50 50 50 - - - % % % adc_lrck frequency (note 18) mclk = 64 fs (1) quad-speed mode fs 100 - 200 khz slave mode adc_sclk period single-speed mode double-speed mode quad-speed mode t sclkw 156 156 78 - - - - - - ns ns ns adc_sclk duty cycle single-speed mode double-speed mode quad-speed mode 45 45 45 - - - 55 55 55 % % % 384x mode (pin 6 = hi) mclk frequency (note 18) internal 1.5 1.536 - 19.2 mhz internal 3 33.024 - 38.4 mhz master mode adc_sclk duty cycle single-speed mode double-speed mode quad-speed mode - - - 50 50 33 - - - % % % adc_lrck frequency (note 18) mclk = 96 fs (1.5) quad-speed mode fs 100 - 200 khz slave mode adc_sclk period single-speed mode double-speed mode quad-speed mode t sclkw 290 193 104 - - - - - - ns ns ns adc_sclk duty cycle single-speed mode double-speed mode quad-speed mode 45 45 45 - - - 55 55 50 % % %
CS42406 25 lrck input sclk input sdout msb t stp t hld t sclkw msb-1 t slrd sclk output sdout lrck output msb msb-1 t sdo t mslr figure 24. master mode, left justified sai figure 25. slave mode, left justified sai sclk output sdout lrck output msb t mslr msb-1 t sdo lrck input sclk input sdout t stp t hld t sclkw msb t slrd figure 26. master mode, i2s sai figure 27. slave mode, i2s sai
CS42406 26 ds614pp5 adc/dac_lrck adc/dac_sclk msb lsb msb lsb aoutax left channel right channel sdout sdinx aoutbx msb ainl ainr figure 28. left justified up to 24-bit data adc/dac_lrck adc/dac_sclk msb lsb msb lsb aoutax left channel right channel sdoutx sdinx aoutbx msb ainl ainr figure 29. i2s, up to 24-bit data adc/dac_lrck adc/dac_sclk msb lsb msb lsb aoutax left channel right channel sdinx aoutbx figure 30. right justified data
CS42406 27 switching specifications - control port interface inputs: logic 0 = gnd, logic 1 = vlc notes: 19. data must be held for sufficient time to bridge the transition time, t fc , of scl. 20. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 21. for single-speed mode, for double-speed mode, for quad-speed mode. parameter symbol min max unit i2c mode scl clock frequency f scl - 100 khz dac_rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 19) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 20) t ack - (note 21) ns 5 2 56 fs ---------------------- - 5 128 fs - --------------------- - 5 64 fs ------------------- - t buf t hdst t low t hdd t high t sud stop st a rt sda scl t irs t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack dac_rst figure 31. control port timing - i2c mode
CS42406 28 ds614pp5 switching specifications - control port interface (continued) notes: 22. t spi only needed before first falling edge of cs after dac_rst rising edge. t spi = 0 at all other times. 23. data must be held for sufficient time to bridge the transition time of cclk. 24. for f sclk < 1 mhz. parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz dac_rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 22) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl -ns cclk high time t sch -ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 23) t dh 15 - ns rise time of cclk and cdin (note 24) t r2 - 100 ns fall time of cclk and cdin (note 24) t f2 - 100 ns 1 mclk ----------------- 1 mclk ----------------- t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs dac_rst figure 32. control port timing - spi mode
CS42406 29 3. typical connection diagram 33 vls gnd CS42406 mc lk va aouta1 1 46 47 7,9 0.01 f 1 f +3.3 v to +5 v 15 10 14 sdin1 2 dif1/scl/cclk dif0/sda/cdin dac_m0/ad0/cs dac_rst mu tec 1 optional mu te circuit 3.3 f 0.01 f aouta1 c = 4 fs(r 560) r l + + 21 22 dac_filt+ dac_vq 13 17 dac_m1 3 dac_lrck dac_sclk sd in 3 sd in 2 3.3 f 10 k ? c 560 ? + 41 40 3.3 f c 560 ? + 39 aoutb1 r l 560 ? optional mu te circuit aouta3 r 3.3 f 10 k ? c 560 ? + 28 30 3.3 f 10 k ? c 560 ? + 29 aoutb3 r load aoutb1 0.01 f 3.3 f aouta3 mutec 3 aoutb3 vd 0.01 f 1 f gnd 8 0.01 f +1.8 v to +5 v vlc 0.01 f +1.8 v to +5 v r load + 560 +3.3 v to +5 v 32 4,45 16 48 5.1 ? * * resistor may only be used if vd is derived from va. if used, do not drive any other logic from vd gnd 31 adc_m0 adc_m1 44 43 6 adc_384x/256x adc_pdn 18 1 f 0.01 f 34 25 adc_filt+ adc_vq 0.01 f 22 f 12 11 5 adc_lrck adc_sclk sdout analog input buff er ainr ainl 26 24 ** pu ll- u p to v l s f o r i 2 s pu ll- do w n to gnd f o r l j vls or gnd** c / mode c onf iguration digital audio aouta2 r l aoutb2 r l 38 mu tec2 3.3 f 10 k ? c + 37 3.3 f 10 k ? c 560 ? + 36 aouta2 aoutb2 optional mu te circuit 10 k ? 10 k ? load load figure 33. typical connection diagram
CS42406 30 ds614pp5 4. applications 4.1 single, double, and quad-speed modes 4.1.1 adc serial port the adc?s internal to the CS42406 can support output sample rates from 2 khz to 200 khz, and a base mclk/adc_lrck ratio of either 256x or 384x. the proper speed mode can be determined by the desired output sample rate and the external mclk/adc_lrck ratio, as shown in table 1 and table 2. please see section 4.2 for a discussion on how to select the desired speed mode. * quad-speed mode, 64x only available in master mode. table 1. adc speed modes and the associated output sample rates (fs) for 256x mode * quad speed mode, 96x only available in master mode. table 2. adc speed modes and the associated output sample rates (fs) for 384x mode 4.1.2 dac serial port 4.1.2a stand alone mode the dac?s internal to the CS42406 operate in one of four operational modes determined by the dac_mx pins when in stand alone mode. sample rates outside the specified range for each mode are not support- ed. refer to table 3. speed mode mclk / adc_lrck ratio adc_sclk / adc_lrck ratio output samp le rate range (khz) single-speed mode 512x 32x, 48x, 64x 43 - 50 256x 32x, 48x, 64x 2 - 50 double-speed mode 256x 32x, 48x, 64x 86 - 100 128x 32x, 48x, 64x 50 - 100 quad-speed mode 128x 32x, 48x, 64x 172 - 200 64x* 64x 100 - 200 speed mode mclk/adc_lrck ratio adc_sclk/adc_ lrck ratio output sample rate range (khz) single-speed mode 768x 32x, 48x, 64x 43 - 50 384x 32x, 48x, 64x 2 - 50 double-speed mode 384x 32x, 48x 86 - 100 192x 32x, 48x 50 - 100 quad-speed mode 192x 32x, 48x 172 - 200 96x* 48x 100 - 200
CS42406 31 4.1.2b control port mode the dac?s operate in one of three operational modes determined by the fm bits (see section 6.1.4) in control port mode. sample rates outside the specified range for each mode are not supported. 4.2 adc serial port operation as either a clock master or slave the CS42406 adc serial port supports operation as either a clock master or slave. as a clock master, the adc_lrck and adc_sclk pins are outputs with the left/right and serial clocks synchronously generated on-chip. as a clock slave, the adc_lrck and adc_sclk pins are inputs and require the left/r ight and serial clocks to be externally generated. the selection of clock master or slave is made via the adc_mx pins as shown in table 5. 4.2.1 operation as a clock master as a clock master, adc_lrck and adc_sclk operate as outputs. the left/right and serial clocks are internally derived from the master clock with the left/right clock equal to fs and the serial clock equal to 64x fs, as shown in figure 34. dac_m1 dac_m0 input sample rate (fs) mode 0 0 4 khz - 50 khz single-speed mode (without de-emphasis) 0 1 32 khz - 48 khz single-speed mode (with de-emphasis) 1 0 50 khz - 100 khz double-speed mode 1 1 100 khz - 200 khz quad-speed mode table 3. CS42406 stand alone dac operational modes fm1 fm0 input sample rate (fs) mode 0 0 4 khz - 50 khz single-speed mode 0 1 50 khz - 100 khz double-speed mode 1 0 100 khz - 200 khz quad-speed mode 1 1 reserved reserved table 4. CS42406 control port dac operational modes adc_m1 adc_m0 mode 0 0 clock master, single-speed mode 0 1 clock master, double-speed mode 1 0 clock master, quad-speed mode 1 1 clock slave, all speed modes table 5. CS42406 adc serial port mode control
CS42406 32 ds614pp5 4.2.2 operation as a clock slave adc_lrck and adc_sclk operate as inputs in clock slave mode. it is recommended that the left/right clock be synchronously derived from the master clock and must be equal to fs. it is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x fs to maximize system performance. please refer to table 1 and table 2 for supported sclk ratios. a unique feature of the CS42406 adc serial port is the automatic selection of either single, double or quad-speed mode when operating as a clock slave. the auto-mode selection feature supports all standard audio sample rates from 2 to 200 khz. however, there are ranges of non-standard audio sample rates that are not supported when op- erating with a fast mclk (512x/768x, 256x/384x, 128x/192x for single, double, and quad-speed modes, respec- tively). please refer to table 1 and table 2 for supported sample rate ranges. 4.3 digital interface format 4.3.1 dac serial port the CS42406 dac serial port will accept audio samples in 1 of 4 digital interface formats in stand alone mode (as illustrated in table 6), and 1 of 6 formats in control port mode (as illustrated in table 7 on page 41). 128 256 64 adc_m0 adc_m1 adc_lrck output (equal to fs out ) single speed quad speed double speed 00 01 10 2 4 1 adc_sclk output single speed quad speed double speed 00 01 10 1.5 1 0 1 mclk auto-select 2 3 0 1 auto-select 0 1 adc_384x/256x figure 34. adc serial port, master mode clocking
CS42406 33 4.3.1a stand alone mode the desired format for the dac serial port is selected via the dif1 and dif0 pins. for an illustration of the required relationship between the dac_lrck, dac_sclk and sdinx, see figures 28-30. 4.3.1b control port mode the desired format for the dac serial port is selected via the dif2, dif1 and dif0 bits in the mode control 2 register (see section 6.1.2). for an illustration of the required relationship between dac_lrck, dac_sclk and sdinx, see figures 28-30. 4.3.2 adc serial port the CS42406 adc serial port supports both i2s and left justified serial audio formats. upon start-up, the CS42406 will detect the logic level on sdout. a 10 k ? pull-up resistor to vls is needed to select i2s format, and a 10 k ? pull-down resistor to gnd is needed to select left justified format. please see figures 28 and 29 for an illustration of the required relationship between adc_lrck, adc_sclk, and sdout. 4.4 de-emphasis control the CS42406 includes on-chip digital de-emphasis. figure 35 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. notes: de-emphasis is only available in single-speed mode. 4.4.1 stand alone mode the operational mode pins, dac_m1 and dac_m0, selects the 44.1 khz de-emphasis filter. please see section 4.1.2a for the desired de-emphasis control. 4.4.2 control port mode the mode control bits selects either the 32, 44.1, or 48 khz de-emphasis filter. please see section 6.1.3 for the desired de-emphasis control. dif1 dif0 description format figure 00 left justified, up to 24-bit data 029 01 i2s, up to 24-bit data 128 10 right justified, 16-bit data 230 11 right justified, 24-bit data 330 table 6. dac digital interface format - stand alone mode gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 35. de-emphasis curve
CS42406 34 ds614pp5 4.5 analog connections the analog modulator samples the input at 6.144 mhz. the digital filter will reject signals within the stop- band of the filter. however, there is no rejection for input signals which are multiples of the input sampling frequency (n * 6.144 mhz), where n=0, 1, 2, ... refer to figure 36 which shows the suggested filter that will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. 4.5.1 capacitor size on the reference pin (filt+) the CS42406 requires an external capacitance on the internal reference voltage pin, adc_filt+. the size of this decoupling capacitor will affect the low frequency distortion performance as shown in figure 37, with larger capacitor values used to optimize low frequency distortion performance. *place as close to the CS42406 as possible. va + - 4.7 f 100 k ? 100 k ? 470 pf c0g 634 ? 91 ? 2200 pf c0g ainl ainr CS42406 input1 va + - 4.7 f 100 k ? 100 k ? 470 pf c0g 634 ? 91 ? 2200 pf c0g input2 * * figure 36. CS42406 recommended analog input buffer 47 uf 100 uf 22 uf 10 uf 6.8 uf 4.7 uf 3.3 uf 2.2 uf 1 uf 5.6 uf figure 37. CS42406 adc: thd+n versus frequency
CS42406 35 4.6 recommended power-up sequence 4.6.1 stand alone mode 1) hold dac_rst and adc_pdn low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies. in this state, the control port is reset to its default settings. 2) bring dac_rst and adc_pdn high. the CS42406 dac will remain in a low power state with dac_vq low and will initiate the stand alone power-up sequence after approximately 512 dac_lrck cycles in single-speed mode (1024 dac_lrck cycles in double-speed mode, and 2048 dac_lrck cycles in quad-speed mode). the CS42406 adc will begin the power-up se- quence immediately following adc_pdn going high. 4.6.2 control port mode 1) hold dac_ rst and adc_pdn low until the power supplies are stable, and the master and left/right clocks are locked to the appropriate frequencies. in this state, the control port is reset to its default settings. 2) bring dac_rst and adc_pdn high. the CS42406 dac will remain in a low power state with dac_vq low. 3) load the desired register settings while keeping the pdn bit set to 1. 4) set the pdn bit to 0. this will initiate the power-up sequence for the dac, which lasts approximately 50 s when the popg bit is set to 0. if the popg bit is set to 1, see section 4.7 for a complete de- scription of power-up timing. 4.7 popguard ? transient control the CS42406 uses a technique to minimize the effects of output transients during power-up and power- down. this technology, when used with external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. it is acti- vated inside the CS42406 when the dac_rst pin or pdn bit is enabled/disabled and requires no other external control, aside from choosing the appropriate dc-blocking capacitors. 4.7.1 power-up when the device is initially powered-up, the audio outputs, aoutax and aoutbx, are clamped to gnd. following a delay of approximately 1000 dac_lrck cycles, each output begins to ramp toward the qui- escent voltage. approximately 10,000 dac_lrck cycles later, the outputs reach dac_vq and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient. 4.7.2 power-down to prevent transients at power-down, the CS42406 must first enter its power-down state. when this oc- curs, audio output ceases and the internal output buffers are disconnected from aoutax and aoutbx. in their place, a soft-start current sink is substituted which allows the dc-blocking capacitors to slowly dis- charge. once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 4.7.3 discharge time to prevent an audio transient at the next power-on, the dc-blocking capacitors must fully discharge be- fore turning on the power or exiting the power-down state. if full discharge does not occur, a transient will occur when the audio outputs are initially clamped to gnd. the time that the device must remain in the
CS42406 36 ds614pp5 power-down state is related to the value of the dc-blocking capacitance and the output load. for example, with a 3.3 f capacitor, the minimum power-down time will be approximately 0.4 seconds. 4.8 mute control the mute control pins go high during power-up initialization, reset, muting (see section 6.1.1 and 6.4.1), or if the mclk to dac_lrck ratio is incorrect. these pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended single supply system. use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. please see the cdb42406 data sheet for a suggested mute circuit. 4.9 grounding and power supply arrangements as with any high resolution converter, the CS42406 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 33 shows the recommended power arrangements, with va, vd, vls and vlc connected to clean supplies. if the ground planes are split be- tween digital ground and analog ground, the gnd pins of the CS42406 should be connected to the analog ground plane. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the cdb42406 evaluation board demonstrates the optimum layout and power supply arrangements. 4.9.1 capacitor placement decoupling capacitors should be placed as close to the CS42406 as possible, with the low value ceramic capacitor being the closest. to further minimize impedance, these capacitors should be located on the same layer as the converter. if desired, all supply pins may be connected to the same supply, but a de- coupling capacitor should still be placed on each supply pin and referenced to analog ground. due to the proximity of the two vd pins (pins 7 and 9), one set of decoupling capacitors will be sufficient for the digital supply. please refer to figure 33. 4.10 control port interface the control port is used to load all the internal register settings (see section 6). the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i2c or spi. notes: mclk must be applied during all i2c communication. 4.10.1 memory address pointer (map) the map byte precedes the control port register byte during a write operation and is not available again until after a start condition is initiated. during a read operation the byte transmitted after the ack will con- tain the data of the register pointed to by the map (see sections 4.10.2a and 4.10.2b for write/read de- tails). 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000
CS42406 37 4.10.1a incr (auto map increment) the CS42406 has map auto increment capability enabled by the i ncr bit (the msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if i ncr is set to 1, map will auto increment after each byte is written, allowing block reads or writes of successive registers. default = ?0? 0 - disabled 1 - enabled 4.10.1b map0-3 (memory address pointer) default = ?0000? 4.10.2 i2c mode in the i2c mode, data is clocked into and out of the bi-directional serial control data line, sda, by the serial control port clock, scl. there is no cs pin. pin ad0 enables the user to alter the chip address (001000[ad0][r/w ]) and should be tied to vlc or gnd as required, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. 4.10.2a i2c write to write to the device, follow the procedure below while adhering to the control port timing as described in ?switching specifications - control port interface? on page 27. 1) initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 0. the eighth bit of the address byte is the r/w bit. 2) wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the register to be written. 3) wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4) if the incr bit (see section 4.10.1a) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i2c writes to other registers are desired, it is necessary to repeat the procedure detailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus. 4.10.2b i2c read to read from the device, follow the procedure below while adhering to the control port switching specifi- cations. during this operation it is first necessary to write to the device, specifying the appropriate register through the map. sda scl 001000 ad0 w start ack map 1-8 ack data 1-8 ack stop figure 38. i2c write
CS42406 38 ds614pp5 1) after writing to the map (see section 4.10.1), initiate a repeated start condition to the i2c bus fol- lowed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2) signal the end of the address byte by not issuing an acknowledge. the device will then transmit the contents of the register pointed to by the map. the map will contain the address of the last register written to the map. 3) if the incr bit is set to 1, the device will continue to transmit the contents of successive registers. con- tinue providing a clock but do not issue an ack on the bytes clocked out of the device. after all the desired registers are read, initiate a stop condition to the bus. 4) if the incr bit is set to 0 and further i2c reads from other registers are desired, it is necessary to repeat the procedure detailed from step 1. if no further reads from other registers are desired, initiate a stop condition to the bus. 4.10.3 spi mode in spi mode, data is clocked into the serial control data line, cdin, by the serial control port clock, cclk (see figure 40 for the clock to data relationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 4.10.3a spi write to write to the device, follow the procedure below while adhering to the control port switching specifica- tions. 1) bring cs low. 2) the address byte on the cdin pin must then be 00100000. 3) write to the memory address pointer, map. this byte points to the register to be written. 4) write the desired data to the register pointed to by the map. 5) if the incr bit (see section 4.10.1a) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6) if the incr bit is set to 0 and further spi writes to other registers are desired, it is necessary to bring cs high, and repeat the procedure detailed from step 1. if no further writes to other registers are de- sired, bring cs high. sda scl 001000 ad0 w start ack map 1-8 ack 001000 ad0 r repeated start or aborted w rite ack data 1-8 (pointed to by map) data 1-8 (pointed to by map) ack stop figure 39. i2c read
CS42406 39 map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 40. spi write
CS42406 40 ds614pp5 5. register quick reference addr function 7 6 5 4 3 2 1 0 1h mode control 1 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 default 10000000 2h invert signal reserved reserved inv _b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 00000000 3h mixing control p1 reserved reserved reserved reserved p1atapi3 p1atapi2 p1atapi1 p1atapi0 default 00001001 4h mixing control p2 reserved reserved reserved reserved p2atapi3 p2atapi2 p2atapi1 p2atapi0 default 00001001 5h mixing control p3 reserved reserved reserved reserved p3atapi3 p3atapi2 p3atapi1 p3atapi0 default 00001001 6h volume control a1 a1_mute a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 00000000 7h volume control b1 b1_mute b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 00000000 8h volume control a2 a2_mute a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 00000000 9h volume control b2 b2_mute b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 00000000 0ah volume control a3 a3_mute a3_vol6 a3_vol 5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 00000000 0bh volume control b3 b3_mute b3_vol6 b3_vol 5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 00000000 0ch mode control 2 szc1 szc0 cpen pdn popg freeze reserved snglvol default 10 0 11000
CS42406 41 6. register descriptions note: all registers are read/write in i2c mode and write only in spi, unless otherwise stated. 6.1 mode control 1 (address 01h) 6.1.1 auto-mute (amute) bit 7 default = 1 0 - disabled 1 - enabled function: the CS42406 dac output w ill mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-static dat a will release the mute. de tection and muting is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. the muting function is affected, similar to volume control changes, by the soft and zero cross bits in the power and muting control register. 6.1.2 digital interface format (dif) bit 6-4 default = 000 - format 0 (left justified, up to 24-bit data) function: the required relationship between the dac_lrck, dac_sclk, and sdinx is defined by the digital interface format and the options are detailed in figures 28-30. 76543210 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 10000000 dif2 dif1 dif0 description format figure 000 left justified, up to 24-bit data 028 001 i2s, up to 24-bit data 129 010 right justified, 16-bit data 230 011 right justified, 24-bit data 330 100 right justified, 20-bit data 430 101 right justified, 18-bit data 530 110 reserved -- 111 reserved -- table 7. digital interface formats - control port mode
CS42406 42 ds614pp5 6.1.3 de-emphasis control (dem) bit 3-2 default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. (see figure 35.) note: de-emphasis is only available in single-speed mode. 6.1.4 functional mode (fm) bit 1-0 default = 00 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - reserved function: selects the required range of input sample rates. 6.2 invert signal (address 02h) 6.2.1 invert signal polarity (inv_xx) bit 5-0 default = 0 0 - disabled 1 - enabled function: when enabled, these bits invert the signal polarity for each of their respective channels. 6.3 mixing control pair 1 (channels a1 & b1) (address 03h) mixing control pair 2 (channels a2 & b2) (address 04h) mixing control pair 3 (channels a3 & b3) (address 05h) 76543210 reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 reserved reserved reserved reserved pxatapi3 pxatapi2 pxatapi1 pxatapi0 00001001
CS42406 43 6.3.1 atapi channel mixing and muting (atapi) bit 3-0 default = 1001 - aoutax = l, aoutbx = r (stereo) function: the CS42406 implements the channel mixing functions of the atapi cd-rom specification. refer to table 8 and figure 41 for additional information. note: all mixing functions occur prior to the digital volume control. mixing only occurs in channel pairs. atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 0000 mute mute 0001 mute r 0010 mute l 0011 mute [(l+r)/2] 0100 r mute 0101 r r 0110 r l 0111 r [(l+r)/2] 1000 l mute 1001 l r 1010 l l 1011 l [(l+r)/2] 1100[(l+r)/2] mute 1101[(l+r)/2] r 1110[(l+r)/2] l 1111[(l+r)/2] [(l+r)/2] table 8. atapi decode a channel volume control aout a aout b left channel audio data right channel audio data b channel volume control & mute & mute figure 41. atapi block diagram
CS42406 44 ds614pp5 6.4 volume control (addresses 06h - 0bh) 6.4.1 mute (mute) bit 7 default = 0 0 - disabled 1 - enabled function: the CS42406 dac output converter output will mute when enabled. the quiescent voltage on the output will be retained. the muting function is affected, similar to attenuation changes, by the soft and zero cross bits. the mutecx pins will go active during the mute period if the mute function is enabled for both channels in the pair. 6.4.2 dac volume control (xx_vol) bit 6-0 default = 0 function: the digital volume control registers allow independent control of the signal levels in 1 db increments from 0 to -119 db. volume settings are decoded as shown in table 9. the volume changes are im- plemented as dictated by the soft ramp and zero cross bits. all volume settings less than -119 db are equivalent to enabling the mute bit. 6.5 mode control 2 (address 0ch) 6.5.1 soft ramp and zero cross control (szc) bit 7-6 default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp and zero cross function: immediate change when immediate change is selected all level c hanges will be implemented im mediately in one step. 76543210 xx_mute xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00000000 binary code decimal value volume setting 0001010 10 -10 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 9. example digital volume settings 76543210 szc1 szc0 cpen pdn popg freeze reserved snglvol 10011000
CS42406 45 zero cross zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz input sample rate) if the signal does not encounter a zero crossing. the zero cross function is independent- ly monitored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 dac_lrck periods. soft ramp and zero cross soft ramp and zero cross dictates that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and will be implemented on successive signal zero crossings. the 1/8 db level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz input sample rate) if the signal does not encounter zero crossings. the zero cross function is independently monitored and implemented for each channel. 6.5.2 control port enable (cpen) bit 5 default = 0 0 - disabled 1 - enabled function: the control port will become active and reset to the default settings when this function is enabled. 6.5.3 power down (pdn) bit 4 default = 1 0 - disabled 1 - enabled function: the dac will enter a low-power state when this function is enabled, but the contents of the control registers will be retained in this mode. the powe r-down bit defaults to ?enabled? on power-up and must be disabled before normal operation in control port mode can occur. 6.5.4 popguard? transient control (popg) bit 3 default = 1 0 - disabled 1 - enabled function: the popguard ? transient control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. please see section 4.7 for implementation details.
CS42406 46 ds614pp5 6.5.5 freeze controls (freeze) bit 2 default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to the registers without the changes taking effect until the freeze is disabled. to have multiple changes in the control port registers take effect simulta- neously, enable the freeze bit, make all register changes, then disable the freeze bit. 6.5.6 single volume control (snglvol) bit 0 default = 0 0 - disabled 1 - enabled function: the individual channel volume levels are independently controlled by their respective volume control bytes when this function is disabled. when enabled, the volume on all channels is determined by the a1 channel volume control byte, and the other volume control bytes are ignored.
CS42406 47 7 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog input for a full-scale digital output. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
CS42406 48 ds614pp5 8. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
CS42406 49 9. revision history revision date changes pp1 august 2003 initial release pp2 march 2004 added revision history table. changed ?gain error? from 5% to 10% in the adc analog characteristics. removed ?inter channel? and ?intra channel phase deviation? specification on page 11 and page 16. removed adc & dac filt+ ?output impedance? and ?current source sink? spec- ification on page 19. changed maximum v ol from 13% to 15% on page 20. changed mclk min/max duty cycle from 40/60% to 45/55% on page 23. added figure 37 on page 34. pp3 august 2004 added lead free part numbers. pp4 december 2004 corrected typographical errors. pp5 december 2004 removed automotive part CS42406-dqz ordering availability and performance specifications. added note 3 to 4 on page 8 limiting va, vd and vl operation. modified table ?switching characteristics - adc serial audio port? on page 23 to highlight 256x and 384x mode. added ?adc_lrck frequency?, ?sclk duty cycle (slave mode)? and setup & hold timing specifications in ?switching characteristics - adc serial audio port? on page 23. removed adc_sclk high/low timing and the ?adc_sclk falling to sdout valid? specifications from ?switching characteristics - adc serial audio port? on page 23. modified figures 24 to 27 on page 25 to reflect timing specifications. corrected typical connection diagram, figure 33 on page 29. added adc_sclk/adc_lrck ratio parameters in table 1 to 2 on page 30. changed recommended anti-aliasing capacitor value from 2700 pf to 2200 pf in figure 36 ?CS42406 recommended analog input buffer? on page 34. table 10. revision history
CS42406 50 ds614pp5 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/ important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtai n the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products a re sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringemen t, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manu facture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual pr operty rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your orga- nization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or se- vere property or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, life sup- port products or other critical applications (including medical devices, aircraft systems or components and per- sonal or automotive safety or security devices). inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, in- cluding the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. purchase of i2c components of cirrus logic, inc., or one of its sublicensed associated companies conveys a license under the ph illips i2c patent rights to use those components in a standard i2c system. spi is a trademark of motorola, inc. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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